Register Pressure and Spilling
REFERENCE CONTEXT · CUDA 12.2; RTX 2070 SUPER; Turing sm_75
Core Concept
Registers are thread-private but consume a finite SM-wide register file. Excess live values and dynamically indexed local arrays can enter local memory; local means a private address space, not on-chip storage.
Why It Affects Performance
Too many registers reduce resident blocks and warps. Forcing fewer registers can create local loads and stores with long latency. Optimize stable runtime, not minimum registers or maximum occupancy.
Example or Pseudocode
nvcc -O3 -arch=sm_75 -lineinfo -Xptxas=-v kernel.cu -o kernel
cuobjdump --dump-sass kernel | rg 'LDL|STL'Experiment with register caps, but strict caps may increase spilling.
Profiling and Performance Judgment
Correlate ptxas spill loads/stores, registers/thread, local traffic, occupancy, long_scoreboard, lg_throttle, and duration. Local-memory use can also come from stacks or real local arrays.
Five-Minute Exercise
A uses 96 regs, 25% occupancy, no local traffic, 52 us. B uses 72, 50%, none, 39 us. D uses 40, 75%, 420 MiB local traffic, 68 us. Choose which?
Show answer
B. It improves parallelism without spilling. D has higher occupancy but is slowest because of massive local-memory traffic.