Warp Stalls: Eligible Warps Matter More Than Occupancy
REFERENCE CONTEXT · CUDA 12.2; RTX 2070 SUPER; Turing sm_75
Core Concept
An active warp is resident but not necessarily ready. An eligible warp has its next instruction's dependencies satisfied. Schedulers need eligible warps to fill issue slots.
Why It Affects Performance
High occupancy can still mean every warp waits on memory. Latency hiding comes from both more resident warps (TLP) and independent work within a thread (ILP).
Example or Pseudocode
float s0=0, s1=0, s2=0, s3=0;
s0 = fmaf(x[i0], y[i0], s0);
s1 = fmaf(x[i1], y[i1], s1);Independent accumulator chains improve ILP, but excessive unrolling raises register pressure and can spill.
Profiling and Performance Judgment
Inspect SchedulerStats, WarpStateStats, eligible and issued warps. High long_scoreboard with only 35% peak DRAM can indicate exposed latency rather than saturated bandwidth.
Five-Minute Exercise
Given 75% occupancy, 0.25 eligible warps/scheduler, 35% peak DRAM, and 62% long_scoreboard, what is the likely issue?
Show answer
Insufficient latency hiding. Check coalescing, locality, ILP or prefetching, and spilling rather than only increasing occupancy.